Conference and Workshop Papers

Remote memory in the age of fast networks
Marcos K. Aguilera, Nadav Amit, Irina Calciu, Xavier Deguillard, Jayneel Gandhi, Pratap Subrahmanyam, Lalith Suresh, Kiran Tati, Rajesh Venkatasubramanian, Michael Wei.
SoCC 2017.

Distributed Resource Management across Process Boundaries
Lalith Suresh, Peter Bodik, Ishai Menache, Marco Canini, Florin Ciucu.
SoCC 2017.

Rein: Taming Tail Latency in Key-Value Stores via Multiget Scheduling
Waleed Reda, Marco Canini, Lalith Suresh, Dejan Kostic, Sean Braithwaite.
EuroSys 2017.

Online and Elastic Resource Reservations for Multi-tenant Datacenters
Carlo Fuerst, Stefan Schmid, Lalith Suresh, and Paolo Costa.

C3: Cutting Tail Latency in Cloud Data Stores via Adaptive Replica Selection
Lalith Suresh, Marco Canini, Stefan Schmid, Anja Feldmann

Programmatic Orchestration of WiFi Networks
Julius Schulz-Zander, Lalith Suresh, Nadi Sarrar, Anja Feldmann, Thomas Hühn, Ruben Merz

Towards Programmable Enterprise WLANs with Odin
Lalith Suresh, Julius Schulz-Zander, Ruben Merz, Anja Feldmann, Teresa Vazao
HotSDN 2012.

Posters and demos

BRB: BetteR Batch Scheduling to Reduce Tail Latencies in Cloud Data Stores
Waleed Reda, Lalith Suresh, Marco Canini, Sean Braithwaite.
ACM SIGCOMM 2015. (Poster)

Thor: Energy Programmable WiFi Networks (Best Demo Award)
Roberto Riggio, Cigdem Sengul, Lalith Suresh, Julius Schulz-Zander, Anja Feldmann
IEEE INFOCOM 2013. (Demo)

Demo: Programming Enterprise WLANs With Odin
Lalith Suresh, Julius Schulz-Zander, Ruben Merz, Anja Feldmann
ACM SIGCOMM 2012. (Demo)


Exploiting convergence characteristics to tackle collusion attacks in OLSR
M.S Gaur, Rajbir Kaur, Lalith Suresh, Vijay Laxmi
Security and Communication Networks journal, Wiley Publications, 2012.

NS-3-Click: Click Modular Router Integration for NS-3
Lalith Suresh, Ruben Merz

Collusion Attack Resistance Through Forced MPR Switching in OLSR
Lalith Suresh, Rajbir Kaur, M. S. Gaur, V. Laxmi
IFIP/IEEE Wireless Days 2010.

A Collusion Attack Detection Method for OLSR-based MANETS Employing Scruple Packets
Lalith Suresh, Kaur, R., Gaur, M. S., and Laxmi, V
SIN 2010.

Acceleration of Functional Validation using GPGPU
Lalith Suresh, Navaneeth Rameshan, M.S. Gaur, Mark Zwolinksi, V. Laxmi

EDA Design Flow Acceleration on GPGPUs
Lalith Suresh, Navaneeth Rameshan, Ashwin Narayan, Mark Zwolinski, M. S. Gaur, V. Laxmi, Virendra Singh
DATE 2010. (Poster)

Emerging EDA Applications in GPGPU and Multi-Core Architectures
M.S Gaur, V. Laxmi, Lalith Suresh, R. Navaneeth, Ashwin Narayan
IBM I-CARE 2009. (Poster)